1. Field of the Invention
The present invention relates to a semiconductor device which is capable of operating at a high speed and which includes source-drain regions of LDD structure, and a method for producing the same.
2. Description of the Related Art
Recently, higher integration and higher speed of LSI are required, and a MOS transistor which operates at higher speed and which is further miniaturized is required. However, once a MOS transistor is further miniaturized, there arise problems that withstand voltage of source-drain is lowered, a gate threshold voltage and conductance are varied by hot electron, and inconvenience due to short channel such as punch-through phenomenon is generated.
For example, main cause of variations of various characteristics of a miniaturized N-channel MOS transistor is hot electron in high electric field existing in the vicinity of the drain. Therefore, in order to obtain a high reliability of the N-channel MOS transistor, it is necessary to moderate the electric field in the vicinity of the drain.
The high electric field in the vicinity of the drain exists in a depletion layer from a pinch-off point to the drain, and the maximum electric field exists at metallurgical joint surfaces between a P-type silicon substrate and an N.sup.+ -region of the drain.
A value of the maximum electric field is increased as a variation of impurity distribution is more abrupt. Therefore, if the impurity distribution in the drain is moderated employing LDD (Lightly Doped Drain) structure, the electric field can be moderated.
However, if the LDD structure is employed, an effectual gate length is shortened, so that the punch-through phenomenon, for example, is prone to be generated. Thereupon, in order to suppress the punch-through phenomenon, there is proposed a structure in which a pocket region including impurities having density higher than the substrate is formed. FIG. 1 is a sectional view showing a conventional N-channel MOS transistor having a pocket region.
In the conventional N-channel MOS transistor having a pocket region, field oxide films 42 and a gate insulation film 43 are formed on a P-type silicon substrate 41. A gate electrode 44 consisting of polycrystalline silicon is formed on the gate insulation film 43. A side wall 45 is formed on a side surface of the gate electrode 44.
Further, a low density region 47 in which N-type impurities are introduced at low density is formed at a surface of the silicone substrate 41 beneath the side wall 45. Pocket regions 48 consisting of impurity regions in which P-type impurities are introduced are formed under the low density region 47 and on side to the gate electrode 44 thereof. High density regions 46 into which N-type impurities are introduced at high density are formed at the surface of the silicon substrate 41 under the gate oxide film 43 located between the side wall 45 and the field oxide films 42. The source-drain regions of LDD structure are constituted in this manner.
In the MOS transistor having the pocket regions 48, since depletion layers extended from the source and the drain are suppressed from being spread, the punch-through phenomenon is suppressed.
However, in the conventional MOS transistor having the pocket regions, the pocket region which is the same as that at the side of the drain is provided at the side of the source, so that channel resistance is increased and the electric current which flows through the transistor is lowered.
For this reason, in order to suppress the short channel effect without lowering the electric current capacity, there is proposed an N-channel MOS transistor in which a pocket region is formed on the side of the drain only (Japanese Unexamined Patent Publication (Kokai) No. Hei 9-181307).
However, if the pocket region is formed on the side of the drain only, there is a problem that electric current leaking to the substrate is increased.